With the evolving of semiconductor technologies, semiconductor dies are becoming increasingly smaller. However, more functions need to be integrated into the semiconductor dies. Accordingly, the semiconductor dies need to have increasingly greater numbers of I/O pads packed into smaller areas, and the density of the I/O pads rises quickly. As a result, the packaging of the semiconductor dies becomes more difficult, which adversely affects the yield.
Package technologies can be divided into two categories. One category is typically referred to as wafer level package (WLP), wherein dies on a wafer are packaged before they are sawed. The WLP technology has some advantages, such as greater throughput and lower cost. Further, less under-fill and/or molding compound is needed. However, WLP suffers from drawbacks. As aforementioned, the sizes of the dies are becoming increasingly smaller, and the conventional WLP can only be fan-in type packages, in which the I/O pads of each die are limited to a region directly over the surface of the respective die. With the limited areas of the dies, the number of the I/O pads is limited due to the limitation of the pitch of the I/O pads. For example, if the pitch of the I/O pads is to be decreased, solder bridges may occur. Additionally, under the fixed-ball-size requirement, solder balls must have a certain size, which in turn limits the number of solder balls that can be packed on the surface of a die.
In the other category of packaging, dies are sawed from wafers before they are packaged onto other wafers, and only “known-good-dies” are packaged. An advantageous feature of this packaging technology is the possibility of forming fan-out chip packages, which means the I/O pads on a die can be redistributed to a greater area than the die itself, and hence the number of I/O pads packed on the surfaces of the dies can be increased.
The bonding of dies to wafers includes dielectric-to-dielectric bonding (also referred to as fusion bonding), copper-to-copper bonding, adhesive bonding, and solder bonding. FIG. 1 illustrates a solder bonding scheme, wherein top die 100 is bonded onto bottom die 200 (which may be in a bottom wafer) through solder balls 106, which are placed between bond pads 104 and 204. A reflow is then performed to melt solder balls 106. In the case solder balls 106 are big enough, this bonding process is self-aligned, since the melted solder balls 106 may help the alignments of bond pads 104 to the respective bond pads 204, as is shown in FIG. 2.
In the case copper-to-copper direct bonding is performed, or in the case solder balls 106 are not big enough, there will be no self-alignment effect. Referring to FIG. 3, top die 100 is bonded onto bottom die 200 with bond pads 104 and 204 contacting each other directly, or bonded through very thin solder films (not shown). If bond pads 104 are misaligned to bond pads 204, the misalignment cannot be corrected by the subsequent reflow, if any. Therefore, each of the top dies has to be aligned to the bottom die accurately. This requires that the bonding of each of the top dies be accompanied by an alignment step. The throughput is thus significantly reduced. New bonding methods are thus needed to improve throughput without sacrificing the accuracy of the alignment.